Floating gate type non-volatile semiconductor memory devices are generally known in the art. Commonly assigned U.S. Pat. No. 4,162,504 is an example of such a device. As shown in FIG. 1, the prior art device consists of a source 12 and drain 14 regions formed in a semiconductor substrate 10. On the surface of the substrate 10, between the source 12 and drain 14 regions, a first insulating layer 16 is provided. A floating gate 18 is positioned over a portion of the first insulating layer 16. A second insulating layer 20 is provided above the first insulating layer 16 and the floating gate 18. A conductive layer is placed on the second insulating layer 20 to form the control gate 22. Contacts 24, 26 and 28 are provided to complete the device.
The memory cell shown in FIG. 1 functions as three serially aligned transistors. The first transistor is formed by region I of substrate 10 functioning as a channel for source and drain regions 12 and 14, respectively. Region A of the second insulator 20, along with the portion of the first insulator 16 subtended by region A, function as a gate oxide for gate 22. A second transistor is formed by the floating gate 18, the region of the insulator 16 subtended by gate 18 and channel region II of the semiconductor substrate 10 which contains the source and drain regions 12 and 14, respectively. The third transistor, in series with the other transistors, is formed around channel region III with region A' of the second insulator 20 and the portion of the insulator 16 subtended by region A' functioning as the gate oxide for gate 22. Region B of insulator 20 functions as an inter-level dielectric between the floating and control gates 18 and 22, respectively.
The memory cell is programmed by forming a charge on the floating gate 18 which has the effect of changing the threshold voltage for conduction between source 12 and drain 14. A typical embodiment of the device is one in which region B of insulator 20 is thin enough to allow electron tunneling between the floating gate 18 and the control gate 22. When a negative charge is formed on the floating gate 18, the memory cell is considered to be in the written or programmed state. A writing or programming potential of about -30 volts is applied to the control gate 22 while the source and drain regions 12 and 14, respectively, are maintained at ground or at zero potential. The device may also be programmed by applying -15 volts to the control gate 22 while +15 volts is applied to the drain 14 and the source 12 is allowed to electrically float. The memory cell may then be erased by removing the negative charge that is stored on the floating gate 18. This is done by applying a +30 volts to the control gate 22 while the source and drain 12 and 14, respectively, are at zero or ground potential. The cell can also be erased by providing the control gate 22 with a potential of about +15 volts while maintaining -15 volts on the drain 14 and allowing the source 12 to float. The cell can also be erased by exposure to ultraviolet radiation which will discharge the floating gate 18.
Referring again to FIG. 1, these devices are fabricated by forming a thin first insulating layer 16 on the surface of the semiconductor substrate 10. The layer 16 may be, for example, thermally grown silicon dioxide. The first insulating layer 16 functions as the gate oxide for the floating gate 18 which is later formed.
After the oxide layer 16 is formed, a conductive layer of polycrystalline silicon (polysilicon) is deposited over the gate oxide layer 16. This conductive layer is typically deposited via chemical vapor deposition techniques, doped and patterned to form the floating gate 18.
Once the floating gate 18 has been formed, a second insulating layer 20 is provided over both the gate oxide layer 16 and the floating gate 18. This second insulating layer 20 may also be thermally grown silicon dioxide. Region B of insulator 20 is known as the tunnel oxide.
A polycrystalline silicon layer is then deposited atop the second insulating layer 20. This polycrystalline layer is doped and patterned to form the control gate 22. Source 12 and drain 14 regions are formed in the semiconductor substrate 10 such that they are aligned to the control gate 22. Contacts 24, 26 and 28 are added and a passivating layer (not shown) is deposited to complete the device.
The above-described method has an inherent drawback because the inter-level dielectric region B between the floating gate 18 and the control gate 22 is simultaneously formed when gate oxide regions A and A' are grown. Thus, the thickness of the gate oxide regions A and A' may dictate the thickness of the inter-level dielectric region B or vice versa. It is necessary in the memory cell art to have independent control of the thickness of the inter-level dielectric region B so that the tunnel oxide conduction properties and capacitance between the control gate 22 and the floating gate 18 can be optimized. If non-memory cell transistors are simultaneously being formed, it is also necessary to have independent control of the thickness of the gate oxide for these devices.